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Espressif Systems /ESP32 /RMT /INT_ST

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Interpret as INT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH1_TX_END)CH1_TX_END 0 (CH3_RX_END)CH3_RX_END 0 (CH6_ERR)CH6_ERR 0 (CH6_TX_THR_EVENT)CH6_TX_THR_EVENT

Fields

CH5_TX_END

The interrupt state bit for channel 5’s mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 5.
CH4_TX_END

The interrupt state bit for channel 4’s mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 4.
CH0_TX_END

The interrupt state bit for channel 0’s mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.
CH3_TX_END

The interrupt state bit for channel 3’s mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 3.
CH7_TX_END

The interrupt state bit for channel 7’s mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 7.
CH2_TX_END

The interrupt state bit for channel 2’s mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 2.
CH6_TX_END

The interrupt state bit for channel 6’s mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 6.
CH1_TX_END

The interrupt state bit for channel 1’s mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.
CH5_RX_END

The interrupt state bit for channel 5’s rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 5.
CH0_RX_END

The interrupt state bit for channel 0’s rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.
CH7_RX_END

The interrupt state bit for channel 7’s rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 7.
CH4_RX_END

The interrupt state bit for channel 4’s rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 4.
CH6_RX_END

The interrupt state bit for channel 6’s rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 6.
CH1_RX_END

The interrupt state bit for channel 1’s rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.
CH2_RX_END

The interrupt state bit for channel 2’s rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 2.
CH3_RX_END

The interrupt state bit for channel 3’s rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 3.
CH0_ERR

The interrupt state bit for channel 0’s rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.
CH1_ERR

The interrupt state bit for channel 1’s rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.
CH5_ERR

The interrupt state bit for channel 5’s rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 5.
CH3_ERR

The interrupt state bit for channel 3’s rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 3.
CH7_ERR

The interrupt state bit for channel 7’s rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 7.
CH4_ERR

The interrupt state bit for channel 4’s rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 4.
CH2_ERR

The interrupt state bit for channel 2’s rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 2.
CH6_ERR

The interrupt state bit for channel 6’s rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 6.
CH7_TX_THR_EVENT

The interrupt state bit for channel 7’s rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.
CH1_TX_THR_EVENT

The interrupt state bit for channel 1’s rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.
CH0_TX_THR_EVENT

The interrupt state bit for channel 0’s rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.
CH4_TX_THR_EVENT

The interrupt state bit for channel 4’s rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.
CH3_TX_THR_EVENT

The interrupt state bit for channel 3’s rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.
CH5_TX_THR_EVENT

The interrupt state bit for channel 5’s rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.
CH2_TX_THR_EVENT

The interrupt state bit for channel 2’s rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.
CH6_TX_THR_EVENT

The interrupt state bit for channel 6’s rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data